Design Full Adder Circuit Using Half Adder

Half Adder

Arithmetic circuits

B. HOLDSWORTH BSc (Eng), MSc, FIEE , R.C. WOODS MA, DPhil , in Digital Logic Design (Fourth Edition), 2002

12.2 The half adder

A half adder is used for adding together the two least significant digits in a binary sum such as the one shown in Figure 12.1(a). The four possible combinations of two binary digits A and B are shown in Figure 12.1(b). The sum of the two digits is given for each of these combinations, and it will be noticed for the case A = 1 and B = 1 that the sum is (10)₂ where the 1 generated is the carry to the next stage of the addition. In the sum shown in Figure 12.1(a), a carry is generated in the least significant column and is then added in at the second stage where a further carry is generated. The carry has rippled through two stages of the addition. Carry ripple, through many stages, in adder circuits generates unacceptable delays, and methods are now available to eliminate this problem.

Figure 12.1. (a) Binary addition. The half adder is used for adding together the two least significant bits (dotted) (b) The addition of the four possible combinations of two binary digits A and B (with a carry to the next most significant stage of addition) (c) Truth table for the half adder (d) NAND implementation of the half adder (e) NOR implementation of the half adder

The additions shown in Figure 12.1(b) are tabulated in the truth table (see Figure 12.1(c)). The columns headed A and B display every combination of the two binary digits to be added, while the third and fourth columns are the corresponding tabulations of the sum S and carry C, respectively. The Boolean equations for the sum and carry read directly from the truth table are:

$\begin{array}{l}S=\overline{A}B+A\overline{B}=A\oplus B\\ C=AB\end{array}$

The implementation of the sum and carry functions using NAND and NOR logic is illustrated in Figure 12.1(d) and 12.1(e).

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Digital Building Blocks

Sarah L. Harris , David Harris , in Digital Design and Computer Architecture, 2022

Half Adder

We begin by building a half adder . As shown in Figure 5.1, the half adder has two inputs, A and B, and two outputs, S and C _out. S is the sum of A and B. If A and B are both 1, S is 2, which cannot be represented with a single binary digit. Instead, it is indicated with a carry out C _out in the next column. The half adder can be built from an XOR gate and an AND gate.

Figure 5.1. 1-bit half adder

In a multi-bit adder, C _out is added or carried in to the next most significant bit. For example, in Figure 5.2, the carry bit shown in blue is the output C _out of the first column of 1-bit addition and the input C _in to the second column of addition. However, the half adder lacks a C _in input to accept the C _out of the previous column. The full adder, described in the next section, solves this problem.

Figure 5.2. Carry bit

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Multioperand Addition

Miloš D. Ercegovac , Tomás Lang , in Digital Arithmetic, 2004

Example 3.2

The reduction by columns for m = 8 magnitudes of n = 5 bits is shown in Table 3.4

TABLE 3.4. Example of reduction process.

	i
	6	5	4	3	2	1	0
l=4
ei			8	8	8	8	8
m 3			6	6	6	6	6
hi			0	0	0	1	0
fi			2	2	2	1	1
l=3
ei		2	6	6	6	6	6
m 2		4	4	4	4	4	4
hi		0	0	0	0	1	0
fi		0	2	2	2	1	1
l=2
ei		4	4	4	4	4	4
m1		3	3	3	3	3	3
hi		0	0	0	0	0	1
fi		1	1	1	1	1	0
l=1
ei	1	3	3	3	3	3	3
m0	2	2	2	2	2	2	2
hi	0	0	0	0	0	0	1
fi	0	1	1	1	1	1	0

The resulting array of full-adders and half-adders is shown in Figure 3.21 It has 26 full-adders and 4 half-adders. For the final 2-to-l reduction, a 7-bit CPA is needed.

FIGURE 3.21. Reduction by columns of eight 5-bit magnitudes. Cost of reduction: 26 FAs and 4 HAs.

The delay in the critical path is roughly

3.38 $\begin{array}{l}T=t_{csa.tree}+t_{\mathcal{C}PA}\\ =4t_{fa}+t_{CPA(7)}\end{array}$

The total delay of the scheme consists of the delay of the reduction array and the delay of the final CPA. Since the delay of the CPA depends on the number of bits, a more aggressive reduction might be applied to reduce the precision of the final adder at the expense of additional counters (Exercise 3.22).

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Introduction to Digital Logic Design

Ian Grout , in Digital Systems Design with FPGAs and CPLDs, 2008

Example 3: One-Bit Full-Adder

The full-adder extends the concept of the half-adder by providing an additional carry-in (Cin) input, as shown in Figure 5.21. This is a design with three inputs (A, B, and Cin) and two outputs (Sum and Cout). This cell adds the three binary input numbers to produce sum and carry-out terms.

Figure 5.21. One-bit full-adder cell

The truth table for this design is shown in Table 5.26.

Table 5.26. One-bit full-adder cell truth table

A	B	Cin	Sum	Cout
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

From viewing the truth table, the Sum output is only a logic 1 when one or three (but not two) of the inputs is logic 1. The Boolean expression for this is (in reduced form):

$\text{Sum}=\text{Cin}\oplus (\text{A}\oplus \text{B})$

From viewing the truth table, the Cout output is only a logic 1 when two or three of the inputs is logic 1. The Boolean expression for this is (in reduced form):

$\text{Cout}=(\text{A}\text{.B})+(\text{Cin}\text{.}(\text{A}\oplus \text{B}))$

This can be drawn as a circuit schematic as shown in Figure 5.22.

Figure 5.22. One-bit full-adder circuit schematic

Any number of half- and full-adder cells can be connected together to form an n-bit addition. Figure 5.23 shows the connections for a four-bit binary adder. In this design, there is no Cin input. Inputs A and B are four bits wide, and bit 0 (A(0) and B(0)) are the LSBs.

Figure 5.23. Four-bit binary adder

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Two-Operand Addition

Miloš D. Ercegovac , Tomás Lang , in Digital Arithmetic, 2004

Carry-Ripple Adder

2.1

In the full-adder implementation with two half-adders, the load on the carry-in is larger than the load on other signals. Since the delay of the carry-out signal is affected by this load, it is convenient to reduce it. One possibility is to include an inverter in the carry-in input to the XOR gate producing s_i and to change the XOR to an XNOR. Determine the effect of this modification on the delay of the carry-out signal, using the characteristics of Table 2.4 (average delay).

TABLE 2.4. Characteristics of a family of CMOS gates.

		Propagation Delays
Gate Type	Fanin	tp LH(ns)	tpHL(ns)	tp (average)(ns)	Load Factor (standard loads)	Size (equivalent gates)
AND	2	0.15 +0.037 L	0.16+0.017 L	0.16+ 0.027 L	1.0	2
AND	3	0.20+0.038 L	0.18+0.018 L	0.19+ 0.028 L	1.0	2
AND	4	0.28+0.039 L	0.21+0.019 L	0.25+ 0.029 L	1.0	3
AND	2	0.15 +0.037 L	0.16+0.017L	0.16+ 0.027 L	1.0	2
AND	3	0.20+0.038 L	0.18+0.018 L	0.19+ 0.028 L	1.0	2
AND	4	0.28+0.039 L	0.21+0.019 L	0.25+ 0.029 L	1.0	3
AND	2	0.15 +0.037 L	0.16+0.017L	0.16+ 0.027 L	1.0	1
AND	3	0.20+0.038 L	0.18+0.018 L	0.19+ 0.028 L	1.0	1
AND	4	0.28+0.039 L	0.21+0.019 L	0.25+ 0.029 L	1.0	2
OR	2	0.12+0.037 L	0.20+0.019 L	0.16+ 0.028 L	1.0	2
OR	3	0.12+0.038 L	0.34+0.022 L	0.23+ 0.025 L	1.0	4
OR	4	0.13 +0.038 L	0.45+0.025 L	0.29+ 0.032 L	1.0	5
NOT	1	0.02+0.038 L	0.05+0.017 L	0.04+ 0.028 L	1.0	6
NAND	2	0.05+0.038 L	0.08+0.027 L	0.07+ 0.033 L	1.0	1
NAND	3	0.07+0.038 L	0.09+0.039 L	0.08+ 0.039 L	1.0	2
NAND	4	0.10+0.037 L	0.12+0.051 L	0.11+0.045 L	1.0	4
NAND	5	0.21+0.038 L	0.34+0.019 L	0.28+0.029 L	1.0	4
NAND	6	0.24+0.037 L	0.36+0.019 L	0.30+0.028 L	1.0	5
NAND	8	0.24+0.038 L	0.42 +0.019 L	0.33+0.029 L	1.0	6
NOR	2	0.06+0.075 L	0.07+0.016 L	0.07+0.046 L	1.0	1
NOR	3	0.16+0.111 L	0.08+0.017 L	0.12+0.059 L	1.0	2
NOR	4	0.23+0.149 L	0.08+0.017 L	0.16+0.083 L	1.0	4
NOR	5	0.38+0.038 L	0.23 +0.018 L	0.32+0.028 L	1.0	4
NOR	6	0.46+0.037 L	0.24+0.018 L	0.35+0.028 L	1.0	5
NOR	8	0.54+0.038 L	0.23+0.018 L	0.39+0.028 L	1.0	6
XOR +	2*	0.30+0.036 L	0.30+0.021 L	0.30+0.029 L	1.1	3
		0.16+0.036 L	0.15+0.020 L	0.15+0.028 L	2.0
XOR +	3*	0.50+0.038 L	0.49+0.027 L	0.50+0.033 L	1.1	6
		0.28+0.039 L	0.27+0.027 L	0.28+0.033 L	2.4
		0.19+0.036 L	0.17+0.025 L	0.18+0.032 L	2.1
2-OR/NAND 2	4	0.17+0.075 L	0.10+0.028 L	0.14+0.052 L	1.0	2
2-AND/NOR 2	4	0.17+0.075 L	0.10+0.028 L	0.14+0.052 L	1.0	2
2-MUX	2	0.20+0.050 L	0.22+0.050 L	0.21+0.050 L	0.5	2

L

load on the gate output

*

different characteristics for each input

+

XNOR same characteristics as XOR; for full-adder characteristics see Table 2.2

2.2

Determine the delay of a 32-bit adder using the full-adder characteristics of Table 2.4 (average delays).

2.3

Design a radix-4 full adder using the CMOS family of gates shown in Table 2.4. Compare delay and size with a 2-bit carry-ripple adder implemented with (radix-2) full-adders (use average delays).

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Introduction to Digital Logic Design with VHDL

Ian Grout , in Digital Systems Design with FPGAs and CPLDs, 2008

6.14.3 One-Bit Half-Adder

An important logic design created from the basic logic gates is the half-adder, shown in Figure 6.39, which has two inputs (A and B) and two outputs (Sum and Carry-Out (Cout)). This cell adds the two binary input numbers and produces sum and carry-out terms.

Figure 6.39. Half-adder cell

The truth table for this design is shown in Table 6.8.

Table 6.8. Half-adder cell truth table

A	B	Sum	Cout
0	0	0	0
0	1	1	0
1	0	1	0
1	1	0	1

The Sum output is only a logic 1 when either but not both inputs are logic 1:

This is actually the Exclusive-OR function, so:

The Cout output is logic 1 only when all two inputs are logic 1 (i.e., A AND B):

This can be drawn as a logic diagram as shown in Figure 6.40.

Figure 6.40. Half-adder logic diagram

A dataflow VHDL description for the one-bit half-adder that uses the two logic expressions is shown in Figure 6.41. Here, two expressions are placed in the architecture body (one expression for the Sum output on line 17, the second for the Cout output on line 18).

Figure 6.41. VHDL code for a one-bit half-adder

An example VHDL test bench for this design is shown in Figure 6.42.

Figure 6.42. VHDL test bench for a one-bit half-adder

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Digital electronics

Martin Plonus , in Electronics and Communications for Scientists and Engineers (Second Edition), 2020

7.4.3 The full adder

For general addition an adder is needed that can also handle the carry input. Such an adder is called a full adder and consists of two half-adders and an OR gate in the arrangement shown in Fig. 7.14a . If, for example, two binary numbers A  =   111 and B  =   111 are to be added, we would need three adder circuits in parallel, as shown in Fig. 7.14b, to add the 3-bit numbers. As a carry input is not needed in the least significant column (A _o , B _o ), a half-adder is sufficient for this position. All other positions require a full adder. The top row in Fig. 7.14b shows the resultant sum 1110 of the addition of the two numbers A and B. Note that for the numbers chosen the addition of each column produces a carry of 1. The input to the half-adder is digits from the first column, A _o   =   1 and B _o   =   1; the input to the adjacent full adder is a carry C _o   =   1 from the half-adder and digits A ₁  =   1 and B ₁  =   1 from the second column, which gives C ₁  =   1 and S ₁ as the output of the first full adder. Ultimately the sum C ₂ S ₂ S ₁ S _o   =   1110 is produced.

Fig. 7.14. (a) The circuit of a full adder designed to handle an input carry C _i . (b) An adder which can add two 3-bit numbers A and B. The sum is given as C ₂ S ₂ S ₁ S ₀.

For the addition of large numbers such as two 32-bit numbers, 32 adders are needed; if each adder requires some 7 logic gates, about 224 logic gates are required to add 32-bit numbers. Clearly such a complexity would be unwieldy were it not for integrated circuits, which are quite capable of implementing complex circuitry in small-scale form.

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"Traditional" Design Flows

Clive Max Maxfield , in FPGAs: Instant Access, 2008

Use Constants Wisely

Adders are the most used of the more complex operators in a typical design. In certain cases, ASIC designers sometimes employ special versions using combinations of half-adders and full-adders. This may work very efficiently in the case of a gate array device, for example, but it will typically result in a very bad FPGA implementation.

When using an adder with constants, a little thought goes a long way. For example, "A + 2" can be implemented more efficiently as "A + 1 with carry-in," while "A – 2" would be better implemented as "A – 1 with carry-in."

Similarly, when using multipliers, "A * 2" can be implemented much more efficiently as "A SHL 1" (which translates to "A shifted left by one bit"), while "A * 3" would be better implemented as "(A SHL 1) + A."

In fact, a little algebra also goes a long way in FPGAs. For example, replacing "A * 9" with "(A SHL 3) + A" results in at least a 40-percent reduction in area.

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Processing Elements

Lars Wanhammar , in DSP Integrated Circuits, 1999

Conditional-Sum Adder

The conditional–sum adder generates all possible sums and carries in a manner similar to the carry–select adder [22]. The conditional-sum adder uses a modified half-adder to generate sums and carries in the first phase. The second phase uses log₂(W_d ) levels of multiplexers to conditionally combine neighboring bits into the final sum [36]. This adder can easily be pipelined by placing latches after the first phase and after every multiplexer stage. The conditional–sum adder, implemented using dynamic CMOS circuits [25], is usually faster than a carry–look–ahead adder, but both adders have complex interconnections that require large chip areas. The conditional–sum adder should be considered as a candidate for highspeed CMOS adders.

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Design Full Adder Circuit Using Half Adder

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